This invention is in the field of nonvolatile semiconductor memory. Embodiments of this invention are more specifically directed to non-volatile memory elements of the charge storage type, and that are erasable by ultraviolet light.
Non-volatile solid-state read/write memory devices are now commonplace in many electronic systems, particularly in portable electronic devices and systems. A common technology for realizing non-volatile solid-state memory devices utilizes “floating-gate” transistors to store the data state. In general, trapped electrons on the floating gate raise the apparent threshold voltage of the memory cell transistor (for n-channel devices), as compared with its threshold voltage with no electrons trapped on the floating gate. The stored state can be read by sensing the presence or absence of source-drain conduction under bias.
Because of its convenience and efficiency, modern semiconductor non-volatile memories are now often embedded within larger scale integrated circuits, such as those including modern complex microprocessors, microcontrollers, digital signal processors, and other large-scale logic circuitry. Such embedded non-volatile memory is especially well-suited for use as program memory storing software routines executable by the processor, as well as for use as non-volatile data storage.
As well known in the art, one class of EPROM memory is referred to as UV-erasable EPROM memory, in that the contents of the memory are erasable by exposure to ultraviolet light (i.e., electromagnetic energy, or radiation, that is at ultraviolet wavelengths). According to conventional technology, the memory cell transistor in an EPROM is “programmed” by biasing it so that high energy electrons are injected through a thin dielectric film onto an electrically isolated transistor gate element. A more recent class of memories are referred to as EEPROM (electrically erasable programmable read-only memory), in that the memory cell transistors can be biased to selectively add or remove electrons from the floating gate, by way of a high voltage Fowler-Nordheim tunneling mechanism through a thin gate dielectric. Some EEPROM memory devices are of the “flash” type, in that a large number (a “block”) of memory cells can be simultaneously erased in a single electrical operation. While EEPROMs are electrically erased (and thus typically housed in opaque device packages), EEPROM cells are also erasable by exposure to ultraviolet light in the same manner as UV EPROMs, even though UV light exposure will not be the erasure mechanism in actual system use. Another type of non-volatile electrically-programmable memory is referred to as “one-time programmable” (“OTP”) memories, which can be programmed once, but is not erasable. For example, one type of OTP memory is a UV-erasable EPROM (i.e., not electrically erasable) packaged in an opaque package.
In certain applications, it is essential that programmed non-volatile memory elements not be erased. For example, some semiconductor memory devices, either random access memory (RAM), EPROM, or EEPROM may include programmable EPROM (or EEPROM) memory cells that are used to enable and select “redundant” memory cells in the memory, replacing normal memory array cells that are found to be defective during a manufacturing test. Once programmed, it is of course important that those additional programmable cells not be erased, because the redundant replacement mapping would then be lost. Non-volatile memory cells may also be programmed during manufacture to implement cryptographic information within an integrated circuit, for example to program a “key” or other secret information. In this cryptographic application, conductor lines and circuitry may not be available to re-program the non-volatile cells, and as such erasure would render the circuit non-functional or no longer secure. Non-volatile memory cells may also be provided, in a wide array of integrated circuits, to allow programmable “trimming” of analog voltages and levels; such trimming may be performed during manufacture, in which case erasure of the trimming memory cells would cause device inaccuracy.
Unfortunately, exposure of integrated circuits to ultraviolet light cannot be avoided in many manufacturing processes. For example, some assembly (i.e., packaging) processes require the use of intense ultraviolet light; for example, ultraviolet light is used to release surface mount devices from embossed tape (i.e., “tape and reel”) in system assembly. This ultraviolet light may fully erase the programmed state of one or more cells, or even if not fully erasing a programmed memory cell, may degrade the programmed state of a memory cell to an extent that the operating margin of the circuit is reduced.
In addition, a UV-erasable EPROM may include additional EPROM cells that are used to map particular memory addresses to redundant memory cells (i.e., to replace failed cells at those addresses). Those additional EPROM cells must be protected so that the UV exposure in a conventional erase operation does not also erase the programmed cells mapping that redundant cell association.
The use of an opaque structure within the integrated circuit itself to shield UV-erasable non-volatile memory cells from exposure to light is known in the art. Conventional shield structures protect the memory cells from incident light normal to the active surface, and also from light traveling in a direction that is largely parallel to the active surface. One example of a conventional shielding structure consists of a box-like structure formed of polysilicon or a metal conductor (e.g., aluminum) during the manufacture of the integrated circuit, and disposed over the EPROM cells to be shielded. Conventional UV-shielding structures in integrated circuits typically consist of an opaque “roof” directly overlying the shielded memory cells, in contact with a continuous wall extending around the sides of the shielded memory cells, generally contacting a continuous diffusion ring at the active surface. The walls of these structures are typically formed by way of a continuous contact opening, etched through one or more layers of insulator material (e.g., silicon dioxide) in which a conductive material is deposited to contact diffused regions at the active surface. Openings in the walls of these conventional solid-wall shielding structures are required to allow conductors to pass through. As such, various approaches such as serpentine or labyrinth-like shapes for these conductive opaque shield structures are known.
Chemical-mechanical polishing (“CMP”) is now commonly used in the manufacture of modern complex integrated circuits, as a technique for planarizing the top surface of integrated circuits during manufacture. Such planarization prior to metal deposition has proven useful in avoiding the risk of step coverage failure due to metal conductors running over severe device topology. Planarization prior to metal deposition also facilitates routing of multi-level metal conductors because each metal level is largely constrained in the vertical dimension.
However, it has been observed that conventional UV-shielding structures cannot be reliably formed in process flows that include CMP planarization. In particular, the long continuous contacts and vias required for the solid walls of conventional shielding structures are incompatible with CMP, because of the vulnerability of those structures to “dishing” (i.e., the unintended forming of concave features in metal features within the contact opening). Such dishing can result in a void between an overlying deposited conductor layer and the material filling the contact opening. Excessive formation of particle contaminants has also been observed to be caused by CMP of structures with such long continuous contacts; such particle contaminants in fact corresponding to the material that is dished out from the metal structures. As a result, design rules limiting the length of metal contact openings are now commonly enforced in integrated circuits that are fabricated by process flows including CMP. These design rules are of course incompatible with the formation of conventional UV shield structures with solid metal walls.